From design verification through post-silicon, Sutra plugs into your existing EDA flow and reads spec, RTL, waveform and log as one connected context. It writes testcases and UVM that understand the block they verify, and collapses the four windows engineers normally tab between into a single, hierarchy-aware view.
The bottleneck looks different in every phase of a silicon engagement. The identifier in your query exists in five blocks. The interface you are about to change has consumers no full-text search can enumerate. The spec clauses without assertions never appear in any positive match. None of these are content questions. The answers are relationships the agent has to walk, not text it can match.
Four moments from a single engagement, drawn from a fabless team bringing up
cortex_v3 (a derivative SoC built on cortex_v2 with a new accelerator).
The cast carries from one panel to the next. Use the arrows below, the
dots, or swipe on touch to step through.
Across the industry, teams that adopted general-purpose coding agents over the last year have begun to report that their token spend grew exponentially with engagement size, and that an annual agent budget could be consumed in a single quarter. The cause is structural rather than incidental. A flat-context agent reloads, re-flattens and re-explains the codebase to itself on every session, so the same hierarchy is paid for again and again in tokens. Sutra holds the hierarchy and its cross-references as a persistent knowledge graph, retrieved by structure rather than by string. On multi-block engagements the difference compounds across sessions and reaches an order of magnitude.
The design hierarchy is the first-class object. Spec, RTL, waveform and log hang off the same nodes and are looked up by structure rather than re-flattened into a context window.
Context is held across sessions and across engineers. The model does not pay tokens to rediscover what the team already established yesterday.
Each query pulls the minimum slice of the graph that is relevant to the question, rather than the largest window the model can accept. Sharper context, fewer tokens, fewer wasted iterations.
overflow_chk in alu_top (cortex_v3) handling signed values correctly?
A hierarchy-aware model that still prompts itself like a junior engineer will still answer like one. AI software-engineering agents have learned over the last year that raw model capability matters less than the curated workflow you wrap it in. The same lesson applies, with greater force, to silicon verification, where conventions are denser and "almost right" is indistinguishable from "wrong".
Sutra ships a library of verification skills: prompt scaffolds, generation harnesses and reviewer-passes, authored by experienced verification engineers and invoked at the exact stage of the flow they belong to.
Pulls test intent, corner cases and coverage targets out of the document, the way a lead reads a spec rather than the way a search engine does.
Methodology-correct env, agents, sequencers and scoreboards. Bus-handshake templates per protocol, not boilerplate copied from another project.
Constraints and sequences targeted at the block under test, derived from the corners the spec actually called out.
Missed-bin sampling heuristics and a closure-loop iteration drawn from real coverage-closure engagements.
SVA and assertions drafted from spec clauses, with vacuity and reachability checks built into the pass.
Walks waveform → log → RTL with a senior debugger's heuristics. Lands on a line, cites the spec clause that anchors the expected behaviour.
Lint, style and coverage review applied to every output before it ever reaches you, the way a senior signs off a junior's patch.
Each skill is owned by a domain expert and refined from real engagements.
An engineer normally chases information across four open windows: spec PDF, RTL editor, waveform viewer, and simulation log. Sutra holds the four together as one queryable context. Ask a question in plain English and receive answers grounded in your actual design.
Reads your spec alongside your RTL. Writes testcases that exercise the corner the document called out, rather than generic stimulus.
Generates env, agent, sequencer and scoreboards that match your block's boundary. No copy-paste from another project's testbench.
Ask "why does carry_out fail when op_a is signed?" and Sutra walks the waveform back, lands on the RTL line, and cites the spec clause that defines the expected behaviour.
The same hierarchy carries through to silicon bring-up. Lab logs land on the same nodes your testbench did, so issues are traced back to the right RTL block, not re-investigated from scratch.
"Where else does this signal toggle in the next 200 cycles?" is answered against the actual waveform, scoped to the right module, in seconds.
Inline lint and review for testbench and constraints. Flags untested branches, unused covergroups and missing assertion targets.
Your design never leaves your perimeter. Self-hosted from day one. No outbound calls to anyone's API. Audited for fabless and IDM workflows.
No rip-and-replace. Sutra sits next to your existing simulator, waveform viewer and bug tracker. Use what you already use.
No new IDE to learn, no migration. The existing stages of your verification flow keep their inputs and outputs; Sutra layers a shared context-graph beneath them so each stage can see the others.
PDF · DOCX · Confluence
SV · UVM · constraints
FSDB · FST · VCD · logs
The same hierarchy of nodes is exposed to every stage, persisted across sessions. Each stage queries the others by structure, not by file path.
Most fabless roadmaps run on a small number of lead SoCs, sometimes referred to as driver SoCs, and a longer tail of derivatives built on each. Today every derivative earns its verification collateral again from scratch, because the testbench is wired to a specific block list, address map and corner-case set. Sutra treats the lead's hierarchy as a reusable substrate. When pointed at the derivative's spec and RTL, it computes the structural delta against the parent, carries unchanged collateral forward verbatim, and regenerates only the portions that have actually changed.
Across early-access benchmarks, senior verification engineers using Sutra show consistent 30–60% productivity gains against their own without-Sutra baseline, measured on real blocks rather than toy ones. Full methodology available on request.
Measured across testbench scaffolding, debug turn-around and coverage closure, against each engineer's own historical baseline.
self-controlled · senior engineersGain scales with how hierarchical and cross-referential the block is. Pipeline-heavy designs sit at the top end; flat RTL at the bottom.
benchmark range, not best-caseSutra's team is a mix of senior verification engineers from NXP, Freescale, Uber, Flipkart and Directi. We are currently reaching out to leading engineering institutes for research collaboration.
We invite verification teams to evaluate Sutra on a workload of their choice, from a single block to a complete SoC. Sutra is designed to hold hundreds of specs, RTL files, waveforms and logs together as one queryable context, so the scale of your design is not a constraint. A Sutra engineer pairs with your verification lead through the evaluation, and you receive a quantified report measured on your own design.
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